The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs and, for these advances to be realized, similar developments in IC processing and manufacturing are needed. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component that can be created using a fabrication process) has decreased.
The decreasing geometry sizes may lead to various manufacturing difficulties. For instance, as the device sizes become smaller and smaller, any amount of overlay shift may cause problems. As an example, spacers may be used to define metal lines in an interconnect structure. But if a sufficient overlay requirement is not met during fabrication, the spacers may become damaged during one or more etching processes. The damaged spacers may cause critical dimension uniformity issues for those metal lines, which degrades device performance and may even lead to device failures.
Therefore, while existing methods of patterning semiconductor devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.